16 bits into the segment register…(GS)

software | Windows |

 
These instructions read a full pointer from memory and store it in the
selected segment register:register pair. The full pointer loads 16 bits
 into the segment register SS, DS, ES, FS, or GS


source :
http://pdos.csail.mit.edu/6.828/2008/readings/i386/LGS.htm

software |GNU/Linux|

(gdb) info  registers
rax            0xfffffffffffffdfc	-516
rbx            0x5dc	1500
rcx            0xffffffffffffffff	-1
rdx            0x5dc	1500
rsi            0x1	1
rdi            0x7fff599ac280	140734696702592
rbp            0x1f08af0	0x1f08af0
rsp            0x7fff599ac230	0x7fff599ac230
r8             0x0	0
r9             0xffffffff	4294967295
r10            0x8	8
r11            0x246	582
r12            0x7fff599ac280	140734696702592
r13            0x7fff599ac290	140734696702608
r14            0x0	0
r15            0x1	1
rip            0x7f0129e710c8	0x7f0129e710c8 
eflags         0x246	[ PF ZF IF ]
cs             0x33	51
ss             0x2b	43
ds             0x0	0
es             0x0	0
fs             0x0	0
gs             0x0	0
(gdb)

Instead of FS segment descriptor on x86 versions of the Windows NT
family, GS segment descriptor is used to point to two operating system
defined structures: Thread Information Block (NT_TIB) in user mode
and Processor Control Region (KPCR) in kernel mode. Thus, for example,
in user mode GS:0 is the address of the first member of the Thread
 Information Block. Maintaining this convention made the x86-64 port
 easier, but required AMD to retain the function of the FS and GS
 segments in long mode — even though segmented addressing per se is
 not really used by any modern operating system.[38]

source :
http://en.wikipedia.org/wiki/X86-64

| Related Discussion |

leilei wrote:
I am writting a program for target board which have a 486 cpu, 512K
ram(0x0 to 0x7ffff), 512k flash (0x80000 to 0xFFFFF).My program will
be burned into flash.
My program is to initialize the GDT, IDT, TSS, move them to memory.
Now I can enter protected model and mov GDT, IDT correctly.But when I
am about to mov TSS, some exception came out, and the CPU reset
automaticly. The code casue the problem is like this:
mov cx, gdt_idx
mov gs, cx
when cpu run to the instuction 'mov gs, cx', CPU will reset.
i can assure the value in cx is correctly.

can any one give me some tips about how can this be happend?


This seems to have nothing to do with TSS, yet.
The CPU is not happy with the selector attempted
to load GS with.

Please check that the number in CX is a valid GDT
selector within the table range.

It also seems that there is no handler available
for the exception generated by the segment loading.

--

Tauno Voipio
tauno voipio (at) iki fi

source :
http://coding.derkeiler.com/Archive/General/comp.arch.embedded/2008-04/msg01432.html

| Variation |

I think eax has a typical closer connection to 32 bit software architecture of an operating system and rax is like for 64 bit OS. Link(s). http://lists.xensource.com/archives/html/xen-devel/2006-12/msg00547.html